1. Field of the Invention
The present invention relates to an integrated logic circuit and, more particularly, to a circuit which facilitates a test of a circuit board or other substrates on which semiconductor integrated circuits chips are assembled.
2. Description of the Related Art
FIG. 1 shows a circuit board to which a Boundary-scan technique is applied. In the case of the Boundary-scan technique, a scan path method is utilized to test a plurality of integrated logic circuits on a circuit board. The scan path method is one of method designed to enable testing of semiconductor integrated logic circuits, and is described in IEEE std 1149.1-1990, pp1-5. This description is incorporated in the present specification by way of the reference.
As shown in FIG. 1, four integrated logic circuit chips 52a-52d are arranged on a circuit board 51. Each of the integrated logic circuit chips 52a-52d is provided with internal logic circuits 53a-53d, input/output terminals 58 connected to the integrated logic circuits 52a-52d, and test circuits 56 provided between input/output buffers of the internal logic circuits 53a-53d and the input/output terminals 58.
In a normal operation, the input/output terminals 58 are mutually connected via a signal lines 57 (indicated by thin lines). In a test operation, the scan-in terminal 54 of the circuit board 51 is connected to the scan-in terminal of the integrated logic circuit chip 52a. The scan-out terminals of the integrated logic circuit chips 52a-52c are connected to the scan-in terminals of the integrated logic circuit chips 52b-52d, respectively. The scan-out terminal of the integrated logic circuit chip 52d is connected to the scan-out terminal 55 of the circuit board 51 (Signal lines used in a test operation are indicated by thick lines).
In response to a control signal (not shown) externally supplied when a test operation is performed, the test circuits 56 form a shift register. The shift register serves as a dedicated path for transferring the test data from the scan-in terminal 54 to the scan-out terminal 55.
When the circuit board 51 is tested, the test data is supplied to the scan-in terminal 54 serially and the supplied test data is transferred through the shift registers in synchronism with a clock signal (not shown). When each item of the test data reaches an associated test circuit 56 constituting the shift register, the test data is supplied from the test circuits 56 to the internal logic circuits 53a-53d, which perform predetermined data processing on the supplied test data. The results of the data processing (test results) are supplied to the test circuits 56, transferred through the shift registers in synchronism with the clock signal, and then output to the scan-out terminal 55.
As shown in the circuit shown in FIG. 1, as the number of input/output buffers in the internal logic circuits 53a-53d increases, the number of stages of the shift register constituted by the test circuits 56 increases. When the stages of the shift register are increased, the delay time of the clock signal driving the shift register also increases. Consequently, the timing of data-transfer through the shift register is liable to slow down, with the result that the shift register may operate incorrectly.
This problem will now be described in detail. FIG. 2 shows a part of a circuit equivalent to the shift register constituted by the test circuits 56. In the shift register shown in FIG. 2, pairs of flip-flops and delay circuits are serially connected. The flip-flops 21 and 22 corresponding to the test circuits 56 receive an output data from the preceding flip-flops in synchronism with the clock signal. The delay circuit 23 is formed by a parasitic capacitor and a parasitic inductance of the signal line transmitting the clock signal, and delays the supplied clock signal.
Each of the flip-flops 21 and 22 generally comprises a master-slave flip-flop, as shown in FIG. 3. The master-slave flip-flop shown in FIG. 3 comprises a master latch 41 and a slave latch 42 each having inverters 43 and switches 44a and 44b.
The master latch 41 opens the switch 44a to latch data supplied to the terminal 4a in response to the leading edge of the clock signal supplied to a clock terminal 4c (the trailing edge of the output from the inverter 43). The switch 44b of the slave latch 42 is opened on the trailing edge of the clock signal, so that the slave latch 42 latches the data from the master latch 41 and outputs it to the data output terminal 4b.
FIGS. 4A-4E show timing charts explaining the operation of the flip-flops 21 and 22, wherein the master-slave flip-flop shown in FIG. 3 is used in the same manner as the flip-flops shown in FIG. 2.
In a conventional master-slave flip-flop, the switches 44a and 44b are opened on the leading and trailing edges, respectively. Accordingly, the flip-flop 21 latches the input data D, shown in FIG. 4A, in response to the clock signal C shown in FIG. 4B, and outputs the data D', as shown in FIG. 4C.
Assume now that the clock signal C is changed or deformed by the delay circuit 23 to a signal C', as shown in FIG. 4D, and then supplied to the flip-flop 22. In this case, as shown in FIG. 4E, the flip-flop 22 ignores the high level data 2a output from the flip-flop 21 shown in FIG. 4C. As a result, the data cannot be transferred correctly.